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Dual 10-bit 40MSPS ADC
DESCRIPTION
The WM2124 is a dual channel 10-bit 40MSPS ADC which consumes only 275mW from a single 3.3V supply. The device is optimised for communications applications that require close matching between channels and a wide input bandwidth. Input signals are differential for improved noise performance. Both A and B input channels are sampled simultaneously and are processed through matched signal paths of programmable gain amplifier (PGA) and 10-bit multistage pipeline ADC. A number of different input clock / output data formats are supported including 20-bits wide at the sampling rate or 10-bits wide at twice the sampling rate, with additional clock outputs supplied by the device to latch the output data. System design and power requirements are further simplified by the provision of an on-chip precision voltage reference. Alternatively, external references can be used if higher precision references are required. The device is programmed via a 3-wire serial interface which allows control of PGA gain setting (0 to 18dB range), clock / output data formatting, powerdown control and binary or two's complement number formatting.
WM2124
FEATURES
* * * * Two 10-bit resolution ADCs 40MSPS conversion rate Simultaneous sampling differential input PGAs with 0 to 18dB gain Programmable clock / output data formats - 10-bit multiplexed or 20-bit wide output - Input clock at sample rate or twice sample rate for multiplexed output - Output clocks for output data sampling Precision internal voltage references Programmable via 3-wire serial interface Wide input bandwidth - 300MHz Low power - 275mW typical at 3.3V supplies Powerdown mode to less than 1mW 48-pin TQFP package
* * * * * *
APPLICATIONS
* I/Q demodulation for - Wireless Local Loop (WLL) - Set Top Box (STB) - Cable Modem IF and Baseband Digitisation Test Instrumentation Medical Imaging
* * *
BLOCK DIAGRAM
AVDD AVSS
CSB SDI SCLK CONFIGURATION CONTROL TIMING CONTROL
CLK COUT COUTB DRVDD
AP
AN
+ PGA -
10-Bit ADC
DRVSS
BP
BN
+ PGA -
10-Bit ADC
DATA OUTPUT FORMAT AND OUTPUT BUFFERS
DA[9:0]
DB[9:0]
OEB
STBY PRECISION REFERENCE CIRCUITS
PWDN_REF CML
DVDD
WM2124
REFT REFB
DVSS
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Advance Information, January 2003, Rev 1.2
Copyright 2003 Wolfson Microelectronics plc
WM2124 PIN CONFIGURATION
SCLK DVDD AVDD AVDD DVSS AVSS STBY SDIO OEB CLK AN AP
Advance Information
ORDERING INFORMATION
DEVICE WM2124CFT WM2124IFT
AVSS BN BP PWDNREF CML REFT REFB CSB AVSS AVDD COUT COUTB
TEMP. RANGE 0 to +70oC -40 to +85 C
o
PACKAGE 48-pin TQFP 48-pin TQFP
DRVDD DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DRVSS
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
10 11
12 25 13 14 15 16 17 18 19 20 21 22 23 24
DRVDD DA9
DA8
DA7
DA6
DA5
DA4 DA3
DA2
DA1
DA0
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NAME DRVDD DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DRVSS DRVDD DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DRVSS COUTB COUT AVDD TYPE Supply Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Ground Supply Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Ground Digital Output Digital Output Supply DESCRIPTION Positive digital output driver supply Digital output for Q channel in dual bus mode bit 9 (msb) Digital output for Q channel in dual bus mode bit 8 Digital output for Q channel in dual bus mode bit 7 Digital output for Q channel in dual bus mode bit 6 Digital output for Q channel in dual bus mode bit 5 Digital output for Q channel in dual bus mode bit 4 Digital output for Q channel in dual bus mode bit 3 Digital output for Q channel in dual bus mode bit 2 Digital output for Q channel in dual bus mode bit 1 Digital output for Q channel in dual bus mode bit 0 (lsb) Negative digital output driver supply Positive digital output driver supply Digital output for I (dual bus mode), I/Q (single bus mode) bit 9 (msb) Digital output for I (dual bus mode), I/Q (single bus mode) bit 8 Digital output for I (dual bus mode), I/Q (single bus mode) bit 7 Digital output for I (dual bus mode), I/Q (single bus mode) bit 6 Digital output for I (dual bus mode), I/Q (single bus mode) bit 5 Digital output for I (dual bus mode), I/Q (single bus mode) bit 4 Digital output for I (dual bus mode), I/Q (single bus mode) bit 3 Digital output for I (dual bus mode), I/Q (single bus mode) bit 2 Digital output for I (dual bus mode), I/Q (single bus mode) bit 1 Digital output for I (dual bus mode), I/Q (single bus mode) bit 0 (lsb) Negative digital output driver supply Inverted latch clock output for digital outputs Latch clock output for digital outputs Positive Analogue Supply AI Rev 1.2 January 2003 2
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DRVSS
Advance Information PIN 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 CLK 48 OEB Digital Input NAME AVSS CSB REFB REFT CML PWDNREF BP BN AVSS AVDD AP AM AVSS AVDD STBY DVSS SDIO DVDD SCLK TYPE Ground Digital Input Analogue Input/Output Analogue Input/Output Analogue Output Digital Input Analogue Input Analogue Input Ground Supply Analogue Input Analogue Input Ground Supply Digital Input Ground Digital Input Supply Digital Input Digital Input Negative Analogue Supply Serial interface chip select ADC bottom reference ADC top reference ADC reference common mode level output Powerdown control for internal ADC reference generator Positive input for the B signal channel Negative input for the B signal channel Negative Analogue Supply Positive Analogue Supply Positive input for the A signal channel Negative input for the A signal channel Negative Analogue Supply Positive Analogue Supply Standby control Negative Digital Supply Serial interface data input/output Positive Digital Supply Serial interface clock DESCRIPTION
WM2124
Conversion clock. The input is sampled on each rising edge of CLK when using a 40MHz input and alternate rising edges when using an 80MHz clock. Output enable. A LOW on this terminal will enable the data output bus, COUT and COUTB
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage, DVDD to DVSS Digital output driver supply voltage, DRVDD to DRVSS Analogue supply voltage, AVDD to AVSS Maximum ground difference between AVSS, DVSS and DRVSS Voltage range digital inputs Voltage range analogue inputs (includes CLK pin) Operating temperature range, TA Storage temperature Lead temperature (1.6mm from case for 10 seconds)
MIN -0.5V -0.5V -0.5V -0.5V DVSS - 0.5V AVSS - 0.5V -45C -65C
MAX +3.6V +3.6V +3.6V +0.5V DVDD + 0.5V AVDD + 0.5V +85C +150C +300C
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WM2124 RECOMMENDED OPERATING CONDITIONS
PARAMETER Power Supply Digital supply range Digital output driver supply range Analogue supply range Ground Analogue and Reference Inputs Reference Input Voltage (top) Reference Input Voltage (bottom) Reference Voltage Differential Reference Input Resistance Reference Input Current Analogue Input Voltage (differential) Analogue Input Voltage (single ended) Note 1 Analogue Input Capacitance Clock Input Note 2 Analogue Outputs CML Voltage CML Output Resistance Digital Inputs High-Level Input Voltage Low-Level Input Voltage Input Capacitance Clock Period Pulse Duration Clock Period Pulse Duration Notes 1. 2. Applies only when the signal reference input connects to CML. Clock pin is referenced to AVDD/AVSS. Clock HIGH or LOW Clock HIGH or LOW 12.5 5.25 25 11.25 2.4 DGND 5 AVDD/2 2.3 VREFT VREFB VREFT-VREFB RREF IREF VIN VIN CI -1 CML - 1.0 8 FCLK = 1MHz to 80MHz FCLK = 1MHz to 80MHz FCLK = 1MHz to 80MHz FCLK = 80MHz FCLK = 80MHz 1.9 0.95 0.95 2.0 1.0 1.0 1650 0.62 DVDD DRVDD AVDD DVSS, DRVSS, AVSS 3.0 3.0 3.0 3.3 3.3 3.3 0 SYMBOL TEST CONDITIONS MIN NOM
Advance Information
MAX 3.6 3.6 3.6
UNIT V V V V
2.15 1.1 1.1
V V V mA V
1 CML + 1.0
V pF V V k
DVDD 0.8
V V pF ns ns ns ns
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WM2124
ELECTRICAL CHARACTERISTICS
Test Conditions: over recommended operation conditions with FCLK = 80MHz and use of internal voltage references, and PGA gain = 0dB, unless otherwise stated. PARAMETER DC Accuracy Integral nonlinearity Differential nonlinearity Zero error (Note 3) Full-Scale error Gain error Missing codes References REFT output voltage REFB output voltage Differential Reference Voltage Power Supplies IDD Operating Supply Current AVDD = DVDD = DRVDD = 3.3V, CL = 10pF, VIN = 3.5MHz, -1dBFS DRVDD DVDD PD PD(STBY) tPD tWU External Reference PWDN_REF = L PWDN_REF = H STDBY = H, CLK held HIGH or LOW AVDD 64 1.7 18 275 240 95 550 40 72 2.2 27 345 300 150 mW uW ms us mA VREFTO VREFBO REFTRERB Absolute Min/Max Values Valid and Tested for AVDD = 3.3V 1.9 0.95 0.95 2.0 1.0 1.0 2.1 1.05 1.05 V V V INL DNL nternal References (Note 1) nternal References (Note 2) AVDD = DVDD = DRVDD = 3.3V External References (Note3) -1.5 -0.9 0.4 0.4 0.12 0.28 0.24 No missing codes guaranteed +1.5 +1.0 LSB LSB % of FS % of FS % of FS SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Power Dissipation Standby Power Power-Up Time for all references from Standby Wake up Time Digital Inputs High-Level Input Current on Digital Inputs incl. CLK Low-Level Input Current on Digital Inputs incl. CLK Digital Outputs High-Level Output Voltage
IIH IIL
AVDD = DVDD = DRVDD = 3.6V
-1 -1
+1 +1
uA uA
VOH
AVDD = DVDD = DRVDD = 3.0V at IOH = 50uA, Digital Outputs Forced HIGH AVDD = DVDD = DRVDD = 3.0V at IOH = 50uA, Digital Outputs Forced LOW
2.8
2.96
V
Low-Level Output Voltage Output Capacitance High-Impedance State Output Current to High-Level High-Impedance State Output Current to Low-Level
VOL CO IOZH IOZL
0.04 5
0.2
V pF
AVDD = DVDD = DRVDD = 3.6V CLOAD = 10pF, Single-Bus Mode CLOAD = 10pF, Dual-Bus Mode
-1 -1 3 5
+1 +1
uA uA ns ns
Data Output Rise and Fall Time
Notes 1. INL refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs 1/2LSB before the first code transition. The full-scale point is defined as a level 1/2LSB beyond the last code transition. The deviation is measured from the center of each particular code to the best fit line between these two points. AI Rev 1.2 January 2003 5
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WM2124
2.
Advance Information
An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, (i.e., (the last transition level-first transition level)/(2n-2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than -1LSB ensures no mission codes. Zero is defined as the difference in analogue input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2LSB to the bottom reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). Full scale error is defined as the difference in analogue input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 1022 to 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).
3.
DYNAMIC PERFORMANCE (NOTE 1)
Test Conditions: TA = TMIN to TMAX, AVDD = DVDD = DRVDD = 3.3V, fIN = -1dBFS, Internal Reference, fCLK = 80MHz, fS = 40MSPS, Differential Input Range = 2Vp-p, and PGA Gain = 0dB, unless otherwise noted. PARAMETER Dynamic Performance fIN = 3.5MHz Effective number of bits ENOB fIN = 10.5MHz fIN = 20MHz fIN = 3.5MHz Spurious free dynamic range SFDR fIN = 10.5MHz fIN = 20MHz fIN = 3.5MHz Total harmonic distortion THD fIN = 10.5MHz fIN = 20MHz fIN = 3.5MHz Signal to noise ratio SNR fIN = 10.5MHz fIN = 20MHz fIN = 3.5MHz Signal to noise and distortion ratio Analogue Input Bandwidth 2-Tone Intermodulation Distortion A/B Channel Crosstalk A/B Channel Offset Mismatch A/B Channel Full-Scale Error Mismatch Notes 1. 2. These specifications refer to a 25 series resistor and 15pF differential capacitor between A/B+ and A/B- inputs; any source impedance will bring the bandwidth down. Analogue input bandwidth is defined as the frequency at which the sampled input signal is 3dB down on unity gain and is limited by the input switch impedance. IMD SINAD fIN = 10.5MHz fIN = 20MHz See Note 2 F1 = 9.5MHz, F2 = 9.9MHz 57 69 9.3 9.7 9.7 9.6 75 73 70.5 -71 -71 -68 60.5 60.5 60 60 60 60 300 -68 -75 0.016 0.025 1.75 1.0 MHz dBc dBc % of FS % of FS dB dB -66 dB dB bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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Advance Information
WM2124
PGA SPECIFICATIONS
PARAMETER PGA Gain Range Gain Step Size (Note 1) Gain Error (Note 2) Control Bits per Channel Notes 1. 2. Refer to Table 2, PGA Gain Code. Ideal step size: 18.0618dB/31 = 0.5826dB Deviation from ideal. Refer to Table 2, all gain settings. -0.15 0 to 18 0.5826 0.025 +0.5 5 dB dB dB Bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TIMING REQUIREMENTS
PARAMETER Input Clock Rate Conversion Rate Clock Duty Cycle (40MHz) Clock Duty Cycle (80MHz) Output Delay Time Mux Setup Time Mux Hold Time Output Setup Time Pipeline Delay (latency, channels A and B) Pipeline Delay (latency, channels A and B) Pipeline Delay (latency, channel A) Pipeline Delay (latency, channel B) Pipeline Delay (latency, channel A) Pipeline Delay (latency, channel B) Output Hold Time Aperture Delay Time Aperture Jitter Disable Time, OEB Rising to Hi-Z Enable Time, OEB Falling to Valid Data Notes 1. All internal operations are performed at a 40MHz clock rate. td(o) ts(m) th(m) ts(o) td(pipe) td(pipe) td(pipe) td(pipe) td(pipe) td(pipe) th(o) td(a) tj(a) tdis ten CL = 10pF CL = 10pF MODE = 0, SELB = 0 MODE = 1, SELB = 0 MODE = 0, SELB = 1 MODE = 0, SELB = 1 MODE = 1, SELB = 1 MODE = 1, SELB = 1 CL = 10pF 1.5 CL = 10pF 9 1.7 9 SYMBOL fCLK TEST CONDITIONS MIN 1 1 45 42 50 50 9 10.4 2.1 10.4 8 4 8 9 8 9 2.2 3 1.5 5 5 8 8 TYP MAX 80 40 55 58 14 UNIT MHz MSPS % % ns ns ns ns CLK Cycles CLK Cycles CLK Cycles CLK Cycles CLK Cycles CLK Cycles ns ns ps, rms ns ns
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WM2124
SERIAL INTERFACE TIMING
PARAMETER Maximum Clock Rate SCLK Pulse Width HIGH SCLK Pulse Width LOW Setup Time, CSB LOW Before First Negative SCLK Edge CBS High Width Setup Time, 16th Negative SCLK Edge before CSB Rising Edge Setup Time, Data Ready Before SCLK Falling Edge Hold Time, Data Held Valid after SCLK Falling Edge SYMBOL fSCLK tWH tWH tSU(CS_CK) tWH(CS) tSU(C16_CK) tSU(D) tSU(H) MIN 20 25 25 5 10 5 5 5 TYP
Advance Information
MAX
UNIT MHz ns ns ns ns ns ns ns
TIMING OPTIONS
OPERATING MODE 80MHz Input Clock, Dual-Bus Output, COUT = 40MHz 40MHz Input Clock, Dual-Bus Output, COUT = 40MHz 80MHz Input Clock, Single-Bus Output, COUT = 40MHz 80MHz Input Clock, Single-Bus Output, COUT = 80MHz MODE 0 1 0 1 SELB 0 0 1 1 TIMING DIAGRAM FIGURE 1 2 3 4
TIMING DIAGRAMS
Figure 1 Timing Diagram, Dual Bus Output - Option 1
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WM2124
Figure 2 Timing Diagram, Dual Bus Output - Option 2
Figure 3 Timing Diagram, Single Bus Output - Option 1
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WM2124
Advance Information
Figure 4 Timing Diagram, Single Bus Output - Option 2
Figure 5 Serial Data Write.
Table 1 Register Configuration Default (power-up) condition for this register is all bits = 0.The user register is updated on either the first rising edge of SCLK after the 16th falling edge or CSB rising, whichever comes first. Raising CSB before 16 falling SCLK edges have been seen is an incomplete write error and no register update will occur. The PGA gain settings are resynchronised to the internal data conversion clock to avoid data glitches caused by changing gain settings while sampling the inputs. PGA gain control data is applied to the PGAs on the second falling edge of the ADC sample clock (CLK40INT) after a successful register write. This resynchronisation ensures that no analogue glitch occurs even when SCLK is asynchronous to CLK. Note that only the PGA data is resynchronised. The TWOS, MODE, and SELB register bits take effect immediately after a successful register write.
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WM2124
The output data format can either be in Binary Two's Complement output mode or in unsigned binary mode, which affects both A and B channels. TWOS - Binary Two's Complement Mode: 0 - Unsigned Binary 1 - Binary Two's Complement Output.
OUTPUT DATA FORMAT
GAIN (dB) 0 0.5606 1.1599 1.6643 2.3806 2.8703 3.5218 4.0824 4.6817 5.1630 5.8451 6.3903 6.9807 7.6040 8.0497 8.7712 9.2831 9.8272 10.4078 11.0301 11.7005 12.0412 12.7970 13.2208 14.0944 14.5400 15.0666 15.5630 15.1623 16.7229 17.4181 18.0618
PGx4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PGx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
PGx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
PGx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
PGX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 2 PGA DB[0:4], 5-Bit PGA Gain Code for channel A or B
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WM2124 TYPICAL CHARACTERISTICS
Advance Information
At TA = 25oC, AVDD = DVDD = DRVDD = 3.3V, fIN = -0.5dBFS, Internal Reference, fCLK = 80MHz, fS = 40MSPS, Differential Input Range = 2Vp-p, 25 series resistor, and 15pF differential capacitor at A/B+ and A/B- inputs, unless otherwise stated.
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WM2124
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WM2124 DEVICE OPERATION
INTRODUCTION
Advance Information
The WM2124 implements a dual high-speed 10-bit, 40MSPS converter in a cost-effective CMOS process. The differential inputs on each channel are sampled simultaneously. Signal inputs are differential and the clock signal is single-ended. The clock signal is either 80MHz or 40MHz, depending on the device configuration set by the user. Powered from 3.3V, the dual-pipeline design architecture ensures low-power operation and 10-bit resolution. The digital inputs are 3.3V TTL/CMOS compatible. Internal voltage references are included for both bottom and top voltages. Alternatively, the user may apply externally generated reference voltages. In doing so, the input range can be modified to suit the application. The ADC is a 5-stage pipelined ADC with four stages of fully-differential switched capacitor subADC/MDAC pairs and a single sub-ADC in stage five. All stages deliver two bits of the final conversion result. A digital error correction is used to compensate for modest comparator offsets in the sub-ADCs.
SAMPLE AND HOLD AMPLIFIER
Figure 6 shows the internal SHA/SHPGA architecture. The circuit is balanced and fully differential for good supply noise rejection. The sampling circuit has been kept as simple as possible to obtain good performance for high-frequency input signals.
Figure 6. SHA/SHPGA Architecture The analogue input signal is sampled on capacitors CSP and CSN while the internal device clock is LOW. The sampled voltage is transferred to capacitors CHP and CHN and held on these while the internal device clock is HIGH. The SHA can sample both single-ended and differential input signals. The load presented to the AIN pin consists of the switched input sampling capacitor CS (approximately 2pF) and its various stray capacitances. A simplified equivalent circuit for the switched capacitor input is shown in Figure 7. The switched capacitor circuit is modelled as a resistor RIN . fCLK is the clock frequency, which is 40MHz at full speed, and CS is the sampling capacitor. The use of 25 series resistors and a differential 15pF capacitor at the A/B+ and A/B- inputs is recommended to reduce noise.
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WM2124
Figure 7 Equivalent Circuit for the Switched Capacitor Input
ANALOGUE INPUT, DIFFERENTIAL CONNECTION
The analogue input of the WM2124 is a differential architecture that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection will deliver the best performance from the converter. The analogue inputs must not go below AVDD or above AVDD. The inputs can be biased with any common-mode voltage provided that the minimum and maximum input voltages stay within the range AVSS to AVDD. It is recommended to bias the inputs with a common-mode voltage around AVDD/2. This can be accomplished easily with the output voltage source CML, which is equal to AVDD/2. CML is made available to the user to help simplify circuit design. This output voltage source is not designed to be a reference or to be loaded but makes an excellent DC bias source and stays well within the analogue input common-mode voltage range over temperature. Table 3 lists the digital outputs for the corresponding analogue input voltages. DIFFERENTIAL INPUT VIN = (A/B+) - (A/B-), REFT - REFB = 1V, PGA = 0dB Analogue Input Voltage VIN = +1V VIN = 0V VIN = -1V Digital Output Code 3FFH 200H 000H
Table 3 Output Format for Differential Configuration
DC-COUPLED DIFFERENTIAL ANALOGUE INPUT CIRCUIT
Driving the analogue input differentially can be achieved in various ways. Figure 8 gives an example where a single-ended signal is converted into a differential signal by using a fully differential amplifier. The input voltage applied to VOCM of the amplifier shifts the output signal into the desired common- mode level. VOCM can be connected to CML of the WM2124, the common-mode level is shifted to AVDD /2.
Figure 8 Single Ended to Differential Conversion
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WM2124
AC-COUPLED DIFFERENTIAL ANALOGUE INPUT CIRCUIT
Advance Information
Driving the analogue input differentially can be achieved by using a transformer coupling, as illustrated in Figure 9. The centre tap of the transformer is connected to the voltage source CML, which sets the common-mode voltage to AV DD /2. No buffer is required at the output of CML since the circuit is balanced and no current is drawn from CML.
Figure 9 AC-Coupled Differential Input with Transformer
ANALOGUE INPUT, SINGLE ENDED CONFIGURATION
For a single-ended configuration, the input signal is applied to only one of the two inputs. The signal applied to the analogue input must not go below AVSS or above AVDD. The inputs can be biased with any common-mode voltage provided that the minimum and maximum input voltage stays within the range AV SS to AVDD. It is recommended to bias the inputs with a common-mode voltage around AVDD/2. This can be accomplished easily with the output voltage source CML, which is equal to AVDD/2. An example for this is shown in Figure 10.
Figure 10 AC-Coupled, Single-Ended Configuration
The signal amplitude to achieve full-scale is 2Vp-p. The signal, which is applied at A/B+ is centred at the bias voltage. The input A/B- is also centred at the bias voltage. The CML output is connected via a 4.7k resistor to bias the input signal. There is a direct DC-coupling from CML to A/B- while this input is AC-decoupled through the 10uF and 0.1uF capacitors. The decoupling minimizes the coupling of A/B+ into the A/B- path. Table 4 lists the digital outputs for the corresponding analogue input voltages.
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WM2124
Single Ended Input, REFT-REFB = 1V PGA = 0dB Analogue Input Voltage V(A/B+) = VCML +1V V(A/B+) = VCML V(A/B+) = VCML - 1V Digital Output Code 3FFH 200H 000H
Table 4 Output Format for Single Ended Configuration
REFERENCE TERMINALS
The WM2124's input range is determined by the voltages on its REFB and REFT pins. The WM2124 has an internal voltage reference generator that sets the ADC reference voltages REFB = 1V and REFT = 2V. The internal ADC references must be decoupled to the PCB AVSS plane. The recommended decoupling scheme is shown in Figure 11. The common-mode reference voltages should be 1.5V for best ADC performance.
Figure 11 Recommended External Decoupling for the Internal ADC Reference External ADC references can also be chosen. The WM2124 internal references must be disabled by tying PWDN_REF HIGH before applying the external reference sources to the REFT and REFB pins. The common-mode reference voltages should be 1.5V for best ADC performance.
Figure 12 External ADC Reference Configuration
DIGITAL INPUTS
Digital inputs are CLK, SCLK, SDI, CSB, STDBY, PWDN_REF, and OEB. These inputs don't have a pull-down resistor to ground, therefore, they should not be left floating. The CLK signal at high frequencies should be considered as an `analogue' input. CLK should be referenced to AVDD and AVSS to reduce noise coupling from the digital logic. Overshoot/undershoot should be minimized by proper termination of the signal close to the WM2124. An important cause of performance degradation for a high-speed ADC is clock jitter. Clock jitter
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WM2124
Advance Information causes uncertainty in the sampling instant of the ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2 N ) of a signal that needs to be sampled on one hand, and on the other hand the maximum amount of aperture error dtmax that is tolerable. It is given by the following relation:
dtmax=
1 f 2(N+1)
As an example, for a 10-bit converter with a 20MHz input, the jitter needs to be kept less than 7.8ps in order not to have changes in the LSB of the ADC output due to the total aperture error.
DIGITAL OUTPUTS
The output of WM2124 is an unsigned binary or Binary Two's Complement code. Capacitive loading on the output should be kept as low as possible (a maximum loading of 10pF is recommended) to ensure best performance. Higher output loading causes higher dynamic output currents and can, therefore, increase noise coupling into the part's analogue front end. To drive higher loads, the use of an output buffer is recommended. When clocking output data from WM2124, it is important to observe its timing relation to COUT. Please refer to the timing section for detailed information on the pipeline latency in the different modes. For safest system timing, COUT and COUTB should be used to latch the output data (see Figures 1 to 4). In Figure 4, COUT can be used by the receiving device to identify whether the data presently on the bus is from channel A or B.
LAYOUT, DECOUPLING AND GROUNDING RULES
Proper grounding and layout of the PCB on which the WM2124 is populated is essential to achieve the stated performance. It is advised to use separate analogue and digital ground planes that are spliced underneath the IC. The WM2124 has digital and analogue pins on opposite sides of the package to make this easier. Since there is no connection internally between analogue and digital grounds, they have to be joined on the PCB. It is advised to do this at one point in close proximity to the WM2124. As for power supplies, separate analogue and digital supply pins are provided on the part (AVDD /DVDD ). The supply to the digital output drivers is kept separate as well (DRVDD ). Lowering the voltage on this supply to 3.0V instead of the nominal 3.3V improves performance because of the lower switching noise caused by the output buffers. Due to the high sampling rate and switchedcapacitor architecture, the WM2124 generates transients on the supply and reference lines. Proper decoupling of these lines is, therefore, essential.
SERIAL INTERFACE
A falling edge on CSB enables the serial interface, allowing the 16-bit control register date to be shifted (MSB first) on subsequent falling edges of SCLK. The data is loaded into the control register on the first rising edge of SCLK after its 16th falling edge or CSB rising, whichever occurs first. CSB rising before 16 falling SCLK edges have been counted is an error and the control register will not be updated. The maximum update rate is:
f update max =
NOTES
f SCLK 20MHz = = 1.25MHz 16 16
1. Integral Nonlinearity (INL) -- Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs _ LSB before the first code transition. The full-scale point is defined as a level _ LSB beyond the last code transition. The deviation is measured from the centre of each particular code to the true straight line between these two endpoints. 2. Differential Nonlinearity (DNL) -- An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device n under test (i.e., (last transition level - first transition level)/(2 - 2)). Using this definition for DNL
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Advance Information
WM2124
separates the effects of gain and offset error. A minimum DNL better than -1LSB ensures no missing codes. 3. Zero and Full-Scale Error -- Zero error is defined as the difference in analogue input voltage-- between the ideal voltage and the actual voltage--that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to _ LSB to the bottom reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). Full-scale error is defined as the difference in analogue input voltage--between the ideal voltage and the actual voltage--that will switch the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). 4. Analogue Input Bandwidth -- The analogue input bandwidth is defined as the max. frequency of a 1dBFS input sine that can be applied to the device for which a extra 3dB attenuation is observed in the reconstructed output signal. 5. Output Timing -- Output timing td(o) is measured from the 1.5V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output load is not higher than 10pF. Output hold time t h(o) is measured from the 1.5V level of the COUT input rising edge to the 10%/90% level of the digital output. The digital output is load is not less than 2pF. Aperture delay td(A) is measured from the 1.5V level of the CLK input to the actual sampling instant. The OEB signal is asynchronous. OEB timing tdis is measured from the VIH(MIN) level of OEB to the high-impedance state of the output data. The digital output load is not higher than 10pF. OEB timing ten is measured from the VIL(MAX) level of OEB to the instant when the output data reaches VOH(min) or VOL(max) output levels. The digital output load is not higher than 10pF. 6. Pipeline Delay (latency) -- The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available from the ADC pipeline. Once the data pipelines full, new valid output data is provided on every clock cycle. The first valid data is available on the output pins after the latency time plus the output delay time td(o) through the digital output buffers. Note that a minimum td(o) is not guaranteed because data can transition before or after a CLK edge. It is possible to use CLK for latching data, but at the risk of the prop delay varying over temperature, causing data to transition one CLK cycle earlier or later. The recommended method is to use the latch signals COUT and COUTB which are designed to provide reliable setup and hold times with respect to the data out. 7. Wake-Up Time -- Wake-up time is from the power-down state to accurate ADC samples being taken, and is specified for external reference sources applied to the device and an 80MHz clock applied at the time of release of STDBY. Cells that need to power up are the bandgap, bias generator, SHAs, and ADCs. 8. Power-Up Time -- Power-up time is from the power-down state to accurate ADC samples being taken with an 80MHz clock applied at the time of release of STDBY. Cells that need to power up are the bandgap, internal reference circuit, bias generator, SHAs, and ADCs
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WM2124 PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.0 mm)
Advance Information
DM004.C
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Advance Information
WM2124
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Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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